\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/stm32h7xx\+\_\+hal\+\_\+rcc.h File Reference}
\hypertarget{stm32h7xx__hal__rcc_8h}{}\label{stm32h7xx__hal__rcc_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc.h}}


Header file of RCC HAL module.  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+def.\+h"{}}\newline
{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h"{}}\newline
\doxysubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def}{RCC\+\_\+\+PLLInit\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em RCC PLL configuration structure definition. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\+\_\+\+Osc\+Init\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em RCC Internal/\+External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\+\_\+\+Clk\+Init\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em RCC System, AHB and APB busses clock configuration structure definition. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+NONE}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+HSE}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+HSI}~(0x00000002U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+LSE}~(0x00000004U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+LSI}~(0x00000008U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+CSI}~(0x00000010U)
\item 
\#define {\bfseries RCC\+\_\+\+OSCILLATORTYPE\+\_\+\+HSI48}~(0x00000020U)
\item 
\#define {\bfseries RCC\+\_\+\+HSE\+\_\+\+OFF}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+HSE\+\_\+\+ON}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadb8228c9020595b4cf9995137b8c9a7d}{RCC\+\_\+\+CR\+\_\+\+HSEON}}
\item 
\#define {\bfseries RCC\+\_\+\+HSE\+\_\+\+BYPASS}~((uint32\+\_\+t)(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa3288090671af5a959aae4d7f7696d55}{RCC\+\_\+\+CR\+\_\+\+HSEBYP}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadb8228c9020595b4cf9995137b8c9a7d}{RCC\+\_\+\+CR\+\_\+\+HSEON}}))
\item 
\#define {\bfseries RCC\+\_\+\+LSE\+\_\+\+OFF}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+LSE\+\_\+\+ON}~RCC\+\_\+\+BDCR\+\_\+\+LSEON
\item 
\#define {\bfseries RCC\+\_\+\+LSE\+\_\+\+BYPASS}~((uint32\+\_\+t)(RCC\+\_\+\+BDCR\+\_\+\+LSEBYP \texorpdfstring{$\vert$}{|} RCC\+\_\+\+BDCR\+\_\+\+LSEON))
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga1b34d37d3b51afec0758b3ddc7a7e665}{RCC\+\_\+\+HSI\+\_\+\+OFF}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga0bf09ef9e46d5da25cced7b3122f92f5}{RCC\+\_\+\+HSI\+\_\+\+ON}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf4fcacf94a97f7d49a70e089b39cf474}{RCC\+\_\+\+CR\+\_\+\+HSION}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga47ea1a7697d9e3f7eda06b45bc7f4db6}{RCC\+\_\+\+HSI\+\_\+\+DIV1}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga468823398f54d90a0769f9cc24327091}{RCC\+\_\+\+CR\+\_\+\+HSIDIV\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf4fcacf94a97f7d49a70e089b39cf474}{RCC\+\_\+\+CR\+\_\+\+HSION}})
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga38a54d39b6808f476a0a81b47a4f50f8}{RCC\+\_\+\+HSI\+\_\+\+DIV2}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga955d82cf94af28b08afcb83a9f852f2c}{RCC\+\_\+\+CR\+\_\+\+HSIDIV\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf4fcacf94a97f7d49a70e089b39cf474}{RCC\+\_\+\+CR\+\_\+\+HSION}})
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga3280982afa72662f07301844a8272d1e}{RCC\+\_\+\+HSI\+\_\+\+DIV4}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2004eb0292646109b952f098d6f4e96}{RCC\+\_\+\+CR\+\_\+\+HSIDIV\+\_\+4}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf4fcacf94a97f7d49a70e089b39cf474}{RCC\+\_\+\+CR\+\_\+\+HSION}})
\item 
\#define \mbox{\hyperlink{group___r_c_c___h_s_i___config_ga06315b229d36c98402286f0b48f85d99}{RCC\+\_\+\+HSI\+\_\+\+DIV8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1fc0a415e8fd2af09b0fcb0fa2d4c2e9}{RCC\+\_\+\+CR\+\_\+\+HSIDIV}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf4fcacf94a97f7d49a70e089b39cf474}{RCC\+\_\+\+CR\+\_\+\+HSION}})
\item 
\#define {\bfseries RCC\+\_\+\+HSICALIBRATION\+\_\+\+DEFAULT}~(0x40U)         /\texorpdfstring{$\ast$}{*} Default HSI calibration trimming value for \mbox{\hyperlink{group___library__configuration__section_ga3cee03fca286b4756b2df120eaeef227}{STM32\+H7}} rev.\+V and above. (0x20 value for rev.\+Y handled within \mbox{\hyperlink{group___r_c_c___exported___macros_ga7bccced288554b8598110b465701fad0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI\+\_\+\+CALIBRATIONVALUE\+\_\+\+ADJUST}} macro ) \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries RCC\+\_\+\+HSI48\+\_\+\+OFF}~((uint8\+\_\+t)0x00)
\item 
\#define {\bfseries RCC\+\_\+\+HSI48\+\_\+\+ON}~((uint8\+\_\+t)0x01)
\item 
\#define {\bfseries RCC\+\_\+\+LSI\+\_\+\+OFF}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+LSI\+\_\+\+ON}~RCC\+\_\+\+CSR\+\_\+\+LSION
\item 
\#define {\bfseries RCC\+\_\+\+CSI\+\_\+\+OFF}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+CSI\+\_\+\+ON}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3b501eadb2c4fd9aa2a9c32502e5653}{RCC\+\_\+\+CR\+\_\+\+CSION}}
\item 
\#define {\bfseries RCC\+\_\+\+CSICALIBRATION\+\_\+\+DEFAULT}~(0x20U)         /\texorpdfstring{$\ast$}{*} Default CSI calibration trimming value for \mbox{\hyperlink{group___library__configuration__section_ga3cee03fca286b4756b2df120eaeef227}{STM32\+H7}} rev.\+V and above. (0x10 value for rev.\+Y handled within \mbox{\hyperlink{group___r_c_c___exported___macros_ga54e1aa79a9bcfa75e52f2125d45ebb45}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSI\+\_\+\+CALIBRATIONVALUE\+\_\+\+ADJUST}} macro ) \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries RCC\+\_\+\+PLL\+\_\+\+NONE}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+PLL\+\_\+\+OFF}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+PLL\+\_\+\+ON}~(0x00000002U)
\item 
\#define {\bfseries RCC\+\_\+\+PLLSOURCE\+\_\+\+HSI}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+PLLSOURCE\+\_\+\+CSI}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+PLLSOURCE\+\_\+\+HSE}~(0x00000002U)
\item 
\#define {\bfseries RCC\+\_\+\+PLLSOURCE\+\_\+\+NONE}~(0x00000003U)
\item 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVP}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVP1\+EN
\item 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVQ}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVQ1\+EN
\item 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVR}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVR1\+EN
\item 
\#define \mbox{\hyperlink{group___r_c_c___p_l_l1___v_c_i___range_ga649e07af1f144bdba350bf66eae3f632}{RCC\+\_\+\+PLL1\+VCIRANGE\+\_\+0}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc71fddb32b3b613c0c57fba30ab2413}{RCC\+\_\+\+PLLCFGR\+\_\+\+PLL1\+RGE\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___p_l_l1___v_c_i___range_ga057ea6f97d147b8e3addb99a38787fc9}{RCC\+\_\+\+PLL1\+VCIRANGE\+\_\+1}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabb4447b4d3d4630081c8db37e2737112}{RCC\+\_\+\+PLLCFGR\+\_\+\+PLL1\+RGE\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___p_l_l1___v_c_i___range_ga4ca1adbbfac5598d3225a53b9fbebad7}{RCC\+\_\+\+PLL1\+VCIRANGE\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae66558f91af4a6b59d67b7e811a80517}{RCC\+\_\+\+PLLCFGR\+\_\+\+PLL1\+RGE\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___p_l_l1___v_c_i___range_ga60ae9f766f7d9b9b24edf031d02e3927}{RCC\+\_\+\+PLL1\+VCIRANGE\+\_\+3}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf20b768cb4546fb55ad658730a5e0a8}{RCC\+\_\+\+PLLCFGR\+\_\+\+PLL1\+RGE\+\_\+3}}
\item 
\#define {\bfseries RCC\+\_\+\+PLL1\+VCOWIDE}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+PLL1\+VCOMEDIUM}~RCC\+\_\+\+PLLCFGR\+\_\+\+PLL1\+VCOSEL
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+SYSCLK}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+HCLK}~(0x00000002U)
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+D1\+PCLK1}~(0x00000004U)
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+PCLK1}~(0x00000008U)
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+PCLK2}~(0x00000010U)
\item 
\#define {\bfseries RCC\+\_\+\+CLOCKTYPE\+\_\+\+D3\+PCLK1}~(0x00000020U)
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+CSI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga68d58136497ff6a8f082ab58beee4131}{RCC\+\_\+\+CFGR\+\_\+\+SW\+\_\+\+CSI}}
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+HSI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacbac8bae4f0808b3c3a5185aa10081fb}{RCC\+\_\+\+CFGR\+\_\+\+SW\+\_\+\+HSI}}
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+HSE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafb563f217242d969f4355d0818fde705}{RCC\+\_\+\+CFGR\+\_\+\+SW\+\_\+\+HSE}}
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+PLLCLK}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0bda4ab2df66059b731208784012f667}{RCC\+\_\+\+CFGR\+\_\+\+SW\+\_\+\+PLL1}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___system___clock___source___status_ga73bf4d57a74eac57757821bc1e2af64b}{RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+STATUS\+\_\+\+CSI}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9224f51c8ff898d674651e0d1f42cb17}{RCC\+\_\+\+CFGR\+\_\+\+SWS\+\_\+\+CSI}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___system___clock___source___status_ga0d6c2b0b2d59e6591295649853bb2abd}{RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+STATUS\+\_\+\+HSI}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6764639cf221e1ebc0b5448dcaed590a}{RCC\+\_\+\+CFGR\+\_\+\+SWS\+\_\+\+HSI}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___system___clock___source___status_ga3847769265bf19becf7b976a7e908a64}{RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+STATUS\+\_\+\+HSE}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae09a0202f441c1a43e69c62331d50a08}{RCC\+\_\+\+CFGR\+\_\+\+SWS\+\_\+\+HSE}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___system___clock___source___status_ga4f05019ec09da478d084f44dbaad7d6d}{RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+STATUS\+\_\+\+PLLCLK}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga776d54497552ddb777f9bb98a1c6af24}{RCC\+\_\+\+CFGR\+\_\+\+SWS\+\_\+\+PLL1}}
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV1}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV2}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV4}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV8}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV16}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV64}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV64
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV128}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV128
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV256}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV256
\item 
\#define {\bfseries RCC\+\_\+\+SYSCLK\+\_\+\+DIV512}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDCPRE\+\_\+\+DIV512
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV1}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV2}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV4}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV8}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV16}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV64}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV64
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV128}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV128
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV256}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV256
\item 
\#define {\bfseries RCC\+\_\+\+HCLK\+\_\+\+DIV512}~RCC\+\_\+\+CDCFGR1\+\_\+\+HPRE\+\_\+\+DIV512
\item 
\#define {\bfseries RCC\+\_\+\+APB3\+\_\+\+DIV1}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDPPRE\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+APB3\+\_\+\+DIV2}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDPPRE\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+APB3\+\_\+\+DIV4}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDPPRE\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+APB3\+\_\+\+DIV8}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDPPRE\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+APB3\+\_\+\+DIV16}~RCC\+\_\+\+CDCFGR1\+\_\+\+CDPPRE\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+APB1\+\_\+\+DIV1}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE1\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+APB1\+\_\+\+DIV2}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE1\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+APB1\+\_\+\+DIV4}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE1\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+APB1\+\_\+\+DIV8}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE1\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+APB1\+\_\+\+DIV16}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE1\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+APB2\+\_\+\+DIV1}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE2\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+APB2\+\_\+\+DIV2}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE2\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+APB2\+\_\+\+DIV4}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE2\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+APB2\+\_\+\+DIV8}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE2\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+APB2\+\_\+\+DIV16}~RCC\+\_\+\+CDCFGR2\+\_\+\+CDPPRE2\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+APB4\+\_\+\+DIV1}~RCC\+\_\+\+SRDCFGR\+\_\+\+SRDPPRE\+\_\+\+DIV1
\item 
\#define {\bfseries RCC\+\_\+\+APB4\+\_\+\+DIV2}~RCC\+\_\+\+SRDCFGR\+\_\+\+SRDPPRE\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+APB4\+\_\+\+DIV4}~RCC\+\_\+\+SRDCFGR\+\_\+\+SRDPPRE\+\_\+\+DIV4
\item 
\#define {\bfseries RCC\+\_\+\+APB4\+\_\+\+DIV8}~RCC\+\_\+\+SRDCFGR\+\_\+\+SRDPPRE\+\_\+\+DIV8
\item 
\#define {\bfseries RCC\+\_\+\+APB4\+\_\+\+DIV16}~RCC\+\_\+\+SRDCFGR\+\_\+\+SRDPPRE\+\_\+\+DIV16
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+NO\+\_\+\+CLK}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+LSE}~(0x00000100U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+LSI}~(0x00000200U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV2}~(0x00002300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV3}~(0x00003300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV4}~(0x00004300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV5}~(0x00005300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV6}~(0x00006300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV7}~(0x00007300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV8}~(0x00008300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV9}~(0x00009300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV10}~(0x0000\+A300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV11}~(0x0000\+B300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV12}~(0x0000\+C300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV13}~(0x0000\+D300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV14}~(0x0000\+E300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV15}~(0x0000\+F300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV16}~(0x00010300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV17}~(0x00011300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV18}~(0x00012300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV19}~(0x00013300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV20}~(0x00014300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV21}~(0x00015300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV22}~(0x00016300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV23}~(0x00017300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV24}~(0x00018300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV25}~(0x00019300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV26}~(0x0001\+A300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV27}~(0x0001\+B300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV28}~(0x0001\+C300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV29}~(0x0001\+D300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV30}~(0x0001\+E300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV31}~(0x0001\+F300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV32}~(0x00020300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV33}~(0x00021300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV34}~(0x00022300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV35}~(0x00023300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV36}~(0x00024300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV37}~(0x00025300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV38}~(0x00026300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV39}~(0x00027300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV40}~(0x00028300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV41}~(0x00029300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV42}~(0x0002\+A300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV43}~(0x0002\+B300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV44}~(0x0002\+C300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV45}~(0x0002\+D300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV46}~(0x0002\+E300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV47}~(0x0002\+F300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV48}~(0x00030300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV49}~(0x00031300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV50}~(0x00032300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV51}~(0x00033300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV52}~(0x00034300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV53}~(0x00035300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV54}~(0x00036300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV55}~(0x00037300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV56}~(0x00038300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV57}~(0x00039300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV58}~(0x0003\+A300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV59}~(0x0003\+B300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV60}~(0x0003\+C300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV61}~(0x0003\+D300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV62}~(0x0003\+E300U)
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+HSE\+\_\+\+DIV63}~(0x0003\+F300U)
\item 
\#define {\bfseries RCC\+\_\+\+MCO1}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+MCO2}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSI}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+LSE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafe73b3ad484eeecfa1556021677ecf4a}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+\_\+0}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1c7e8d1da534f052ce835f06227a9b7a}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+\_\+1}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+PLL1\+QCLK}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafe73b3ad484eeecfa1556021677ecf4a}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1c7e8d1da534f052ce835f06227a9b7a}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+\_\+1}})
\item 
\#define {\bfseries RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSI48}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad45738e19d9cacd194685869bd6e6945}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+\_\+2}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+SYSCLK}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+PLL2\+PCLK}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga203156a3f57e2c4498999c7901e0defd}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+0}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+HSE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2fdba9682ff474255248f84e6851932a}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+1}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+PLLCLK}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga203156a3f57e2c4498999c7901e0defd}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2fdba9682ff474255248f84e6851932a}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+1}})
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+CSICLK}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae66a07cf6846bbbf597aa8bf877b682a}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+2}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO2\+SOURCE\+\_\+\+LSICLK}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga203156a3f57e2c4498999c7901e0defd}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae66a07cf6846bbbf597aa8bf877b682a}{RCC\+\_\+\+CFGR\+\_\+\+MCO2\+\_\+2}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+1}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}}
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+2}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}}
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+3}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+4}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}}
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+5}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+6}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+7}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+8}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}}
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+9}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+10}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+11}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+12}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+13}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+14}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+15}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga23171ca70972a106109a6e0804385ec5}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE}}
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+LSIRDY}~(0x00000001U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+LSERDY}~(0x00000002U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+HSIRDY}~(0x00000004U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+HSERDY}~(0x00000008U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+CSIRDY}~(0x00000010U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+HSI48\+RDY}~(0x00000020U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+PLLRDY}~(0x00000040U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+PLL2\+RDY}~(0x00000080U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+PLL3\+RDY}~(0x00000100U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+LSECSS}~(0x00000200U)
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+CSS}~(0x00000400U)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+HSIRDY}~((uint8\+\_\+t)0x22)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+HSIDIV}~((uint8\+\_\+t)0x25)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+CSIRDY}~((uint8\+\_\+t)0x28)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+HSI48\+RDY}~((uint8\+\_\+t)0x2D)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+CPUCKRDY}~((uint8\+\_\+t)0x2E)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+D1\+CKRDY}~RCC\+\_\+\+FLAG\+\_\+\+CPUCKRDY   /\texorpdfstring{$\ast$}{*} alias \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+CDCKRDY}~((uint8\+\_\+t)0x2F)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+D2\+CKRDY}~RCC\+\_\+\+FLAG\+\_\+\+CDCKRDY    /\texorpdfstring{$\ast$}{*} alias \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+HSERDY}~((uint8\+\_\+t)0x31)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+PLLRDY}~((uint8\+\_\+t)0x39)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+PLL2\+RDY}~((uint8\+\_\+t)0x3B)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+PLL3\+RDY}~((uint8\+\_\+t)0x3D)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+LSERDY}~((uint8\+\_\+t)0x41)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+LSIRDY}~((uint8\+\_\+t)0x61)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+CDRST}~((uint8\+\_\+t)0x93)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+BORRST}~((uint8\+\_\+t)0x95)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+PINRST}~((uint8\+\_\+t)0x96)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+PORRST}~((uint8\+\_\+t)0x97)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+SFTRST}~((uint8\+\_\+t)0x98)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+IWDG1\+RST}~((uint8\+\_\+t)0x9A)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+WWDG1\+RST}~((uint8\+\_\+t)0x9C)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+LPWR1\+RST}~((uint8\+\_\+t)0x9E)
\item 
\#define {\bfseries RCC\+\_\+\+FLAG\+\_\+\+LPWR2\+RST}~((uint8\+\_\+t)0x9F)
\item 
\#define \mbox{\hyperlink{group___r_c_c___l_s_e_drive___config_gab5fa5b50304710db2d7f6d583a225da3}{RCC\+\_\+\+LSEDRIVE\+\_\+\+LOW}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___r_c_c___l_s_e_drive___config_ga1151beb7f9869e91fe7617936ad0efff}{RCC\+\_\+\+LSEDRIVE\+\_\+\+MEDIUMLOW}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2bf168a5913ecf4eb6eb5f87a825aa58}{RCC\+\_\+\+BDCR\+\_\+\+LSEDRV\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___l_s_e_drive___config_ga295eed1e1368d526fa0f6356ceecbc48}{RCC\+\_\+\+LSEDRIVE\+\_\+\+MEDIUMHIGH}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa9a3c17caf7eb216d874b7cf1d90358e}{RCC\+\_\+\+BDCR\+\_\+\+LSEDRV\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___l_s_e_drive___config_ga90b0854f3813d7ab2781519bfa58fd95}{RCC\+\_\+\+LSEDRIVE\+\_\+\+HIGH}}~RCC\+\_\+\+BDCR\+\_\+\+LSEDRV
\item 
\#define {\bfseries RCC\+\_\+\+STOP\+\_\+\+WAKEUPCLOCK\+\_\+\+HSI}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+STOP\+\_\+\+WAKEUPCLOCK\+\_\+\+CSI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga623e4f1eb613f4793d3d500c1cfd746a}{RCC\+\_\+\+CFGR\+\_\+\+STOPWUCK}}
\item 
\#define {\bfseries RCC\+\_\+\+STOP\+\_\+\+KERWAKEUPCLOCK\+\_\+\+HSI}~(0x00000000U)
\item 
\#define {\bfseries RCC\+\_\+\+STOP\+\_\+\+KERWAKEUPCLOCK\+\_\+\+CSI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabfc89cbee6dc0e89e1c453fbfea80bd2}{RCC\+\_\+\+CFGR\+\_\+\+STOPKERWUCK}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6c173343c4052340b4bb7789b598017e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB3 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga91061f59b5314335cc2ec6f5e0f1ffcb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f95da0bcb204e40ca556b27290a7541}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6608439910ba24a3f1ca91223fef67f2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9027234bedbcf8c33247f2025583cfd9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b7119cdac6401e2a886aaf068e939dd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga96dffcf5a982b89e776d0011e2904c28}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab94e29d67ee313b4fbdbb491114a412e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga759feae123cb720c81a2c51faa5d6f4d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB3 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab468d918278795540903de51f967d3e8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga93863872b8bedab2b9714ad82f672f3d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga146964bf211aad404f4fd87b1a1efd60}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga391d9d9e405207a852309d6ecb1ea774}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3b81e03e55121671bd852bca6a5a4417}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa10a685a46de1822cc3004073ff47f65}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f1420c6464c2c914b150c52ce7e551d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga49fc2c82ba0753e462ea8eb91c634a98}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB1 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1b5c4bd52d8e7c70e105dd415a191afd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab9359545aecbdd372d75527e563004ad}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabdff3922cc5288bd1bad71b42af2ae94}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad2e166f2522304cb62124bd062b21b0d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga569dc8b9e178a8afab2664fdf87f46c5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa97383d7ee14e9a638eb8c9ba35658f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaea3e1b42c6d846c3916a2bc5d37e243f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3d30ef2d25e82ee9edf3a7f68f0db7b7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga50773ad82a48a72fdd36c1f2bc3137cc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaab05e603c9cadd72e4b6397837b46cef}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB1 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad0ccdaf669ea327e80c455db4dc36177}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga891c5f28951eb33a3b14885d48fc25fc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga32eb3f4ab75d2d7d93c3ffa6a006b16e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad790723221a946246f29e28615d51129}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae89d94d6252c79e450623f69eb939ed6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga725d2a38d8519867922438d48a5885cf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1f26d3fd5c29028c02c448e914049a20}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaefc5cc5261b4d21bee09f1aeeb73af83}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga748915f493aebd62dedfb1eaa3224732}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga16fbc8a6891716f91d96e23fd17c01e2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB2 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01b37cc75f9a14a55b9e89e8ccfac8af}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab3fe87c8fac4bdbfbf5b441cd3e4f363}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5d1408c8cb75e7e9c323312789c20c36}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafadfbac9c200b0ebd5f13284a9ec977d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab32b44a18d532de3c3e56187787cfbc8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8f885339c99130e538e4d7474933d470}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa22387070e0730e79f159197258418d2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga061b46c5af3c4421aff467728bd8c591}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga88a09a68000f2fa176584608f3e5a458}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4db4d98f8081cf6642175d0527453331}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB2 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb083459b7bbd56c9b89db59bb75fdc2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga33be86cb93cc96506040300d4758554e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4c50a7953684fba69f1019f5e1e0ac52}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaef2510aa5e44c9e58e52ce8a204160bd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaade9a685b77400ec6d61b77ef4da8b90}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9b17b31dc3e560ead96b7d8a74c8c679}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga81f9c071cb13a6ebd8f73d68e5f69769}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1452ec3e02b74349a6b37a3b5eede8ed}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga385ab0d5536a609f2ae858367f772175}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1fde58d775fd2458002df817a68f486e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB4 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5ad43f3f4d8163d40f7d402ef75d27c5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5ebfeb136612f370950f52306d29b6fd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga74340ce0f556e370aafc2b8ecdf2dd31}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2cba7d47b6aee57d469f1d8972d442f1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga84098c3c8735d401024a1fb762e9527f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0816a01f8153700ff758c8783e84e9e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga041e72359b94f19569e774030fc6ebff}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabe4d1d0276f070b4501a141fd4006d7c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacef87b3ea226e2ffd67c644da64bd387}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae8e5f06bff47402b632f4f76a9113791}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab3971cefc9881ed9e08a8a856712b19a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7083e491e6a1e165d064d199304bd2f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga60be1be419b57dafbbb93df67d68a424}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0fc90c25d35f9b5b5f66961505de1cd4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeaefe364dafdc0c22353969595421422}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad8982750e98b22493ae0677b3021b01b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga84c2248eab0a30bd8f4912233abbf34a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9d4578e9566823639e049fe69cbaba69}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1eb7dd0a520cef518fb624bf7117b7e1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab2a5e42f487ef22caa3db4b6d3d7d196}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga381deab4cd506e7ead767caa129b1332}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f62a00ae551620fefef1d29c7c42ff1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga15f220ac58a1b016d0a44766bdeaa6e7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad1edbd9407c814110f04c1a609a214e4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB4 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2fc8f9dc5f5b64c14c325c45ee301b4f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga528029c120a0154dfd7cfd6159e8debe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7a8a0e334d69163b25692f0450dc569a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2c0dd8ae5cf2026dab691c05f55fa384}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5c997b15dc4bc3fd8e5b43193e4b1a2d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3770796716f63a656285dcfedf8c0651}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8e182ed43301e2586bc198a729b50436}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafeb6b1e331baa9bec58f17682e5488e4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6d1d0104071b2789b3d8984df336aaa6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad41bf810a1372848f680e55e75a0126f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7dba8c9591cfed20e720cf4f218a03db}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2d73b007700fe1576c7965ce677148bd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9b9353035473ac5f144f6e5385c4bebb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5e939d98ecca025c028bd1d837b84c81}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01c2b4166bbcf59a529cd3c5f8b93d76}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga04deb9fe7c5fad8f1644682c1114613f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga843a7fcc2441b978cadacbea548dff93}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga56838183bdecd8b53c8b23bfcad5b28f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9c405e3a8e5219c98d0262e18bd0eed9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4d0a1867a550ff920abbfbd3b9d85a49}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae32f6d9c7c8d2a27e0929c07fc88b4a6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad39f8cf198a2eab33fae7c44e0ad06d1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad2664d304a1a94c33447300f8608f235}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga178f1c263cb2da5067ae93c4256b2b78}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the APB3 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad136e29f8e13d3114f7fa092e3a79aeb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3e791527358dfa556ea20e1c52ec36ed}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB3 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga72a57950dfa0376ec07ae01d6cdaf189}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2e895257faa38376b9cdfcd756909a43}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the APB1 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf62d32fdde03df10072d856515692c8d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf9b08205c361d1779b6c7a3afdb67e7c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab6669f7a9f892e39fb22b349c1afd78d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga669982035ad2dd6cf095fd8b281f9dab}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga92313068bbe6883497ca424b24f31d44}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga72597483d0d6da14553329d2da3ad45e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gade7a5313eb8b50127a40c5c130c7f3e1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga28c0bd63fbc7500f9c209ef42c0931b6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7e1e013e28c2c8049e057d5f797ef077}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga12352adbb876f2b827d6ac3a04d94e26}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga16612e19c1a7d4cd3c601bf2be916026}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga92917b1e3f9bfe30b55ee49fbf5a0f90}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaf50c7d2265d978fab8fbb68a518096d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga34a7bf921d694c001b67dcd531c807a3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4a09294d81a526606fb6e2a8bd8f2955}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga801a26037f0fd4fa1bad78fefe677f89}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaeae5b9e93721dd4e34274600996baeb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7826848ae938c7f59984d12bc883a6f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1c510498725fb0c1245edaae3d9b1e53}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf9c86fbf588ae5fecb93cc2228dd2e73}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7b3fd516eb04132930f2ac69b80eef6c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaa03f5b5b0959fbd6989d04516dafa7e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac55d407e224e9aae78e7a8f8ae55fcbf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaacbeee793dfe93384ba7526eb243f6cc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga503046793c20e98e03e31acbe4810aee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6e71c993204f3f8bccda80231e70c025}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga472f1ec70a704f3ba78d9865b02c5759}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga214e3b2bdfcfde732b66cee97b45ae7c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad2def81b1df0e62cd322ab60b31ba59f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9fb7035f007ec272b725e51018a36b23}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8888dfd8a1e50f8019f581506ec776d8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga44f246a1407fadc350e416e4c3256f6e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1ee14a6e314a50eee7a1a09482a25abf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga865f11c3f70a9b85ebc5f09baf60eec9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga40b70e57e0b7741e6f62d1f2a25b0a3e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga501dca0467cb5d6119144dbab79243f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga492911cce1e54350519e7793c897102b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaed03071c92bed23b141d05c8409893aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb56a85a6424a60da8edc681f3a1c918}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadc6ab93c1c538a7f2ee24a85a6831274}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga79b0ca8505d46580e6fe779c27fe3806}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1edc6c83fbebf8b4265ef9500aa04b04}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5b0866dac14f73ddeafa6308ac447bec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0c7d9a072dd5ad3f28220667001bfc08}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8a95ee8616f039fd0b00b0efa7297e6c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga490a853eae72da96aad5379a6e939dd8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3ebc5988bcf1e2965ed482fd76c67b22}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab015d6340996f59fa36354ddcc10759d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaa44f4d83019efe5a909604812851991}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa0a717493fc9dac209bc1fcd46ac451d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9938ea115b1c865b757f54673ca8c97b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga741b1908bd8c5ba1822dd87d507510a7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga67a011bda249fc860fe44a88f7b03ff6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6df86d9762cf4412f4b8b55ed2db2815}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga79e0040fab0dbda3f643ba92cba9ee83}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad8fec82c1752a782bad6a24309409900}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadc1b2ba58e8fc70fa34826d92ba75253}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadee5016adb1c8b62a5bb05f055859de0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB1 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf6090239db6a8a6917b3f3accea15ed0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga62bee605d886067f86f890ee3af68eb5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga76f0a16fed0812fbab8bf15621939c8b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb273361eaae66c857b5db26b639ff45}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5642c4226ce18792efeca9d39cb0c5e0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7afed5bd30e0175ae5e46e78173b112f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeb7cf0d708375a807c690fbb070298dd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf40a1f6a134b09aaa211ad159e613d1a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9c3c0f83528521d1122fe9436271ec70}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga282522dda9557cf715be3ee13c031a5b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3de049f8b2ad6c2d4561863021f9e2f9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaba34413dd1dc740389e0082d9ebdedba}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad3bbe0639658ed2cc56f8328b26373ea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5addec8b6604857d81c1386cad21c391}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga76b47e85a8669651c01256ec11ebdc3f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb2b7e20045558372779949fb841ae00}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7570e5654fd61b44dabe0546e524c906}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2ae540056d72f4230da38c082b6c34c1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae291bd8b020dff7ea7f52fec61aa3f9d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeeda9e9945cc58b67cfc877118fea250}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8ae71742361cf64ff099b376a21d673b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf6beaa399462e32b4052ff3428f17710}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab3b6d673061453f062ba13bf6a28742a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadeca04d4641a3c80d8f98617696be2c6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa2d4182170cc81b243393234865643ed}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gada470e2d6874bacb973e385ed245ccc5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga33d8c2c5cfcbf24dbdc5bb7086e97f7f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5cab1955b55c48026c02fe61681d3036}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacaaa75c78c8ef4cf85f30fb20d522054}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga50f8e043a42eaf534c1efa2477078c0a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga30913be6e4b95cf2ebdf79647af18f34}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacbe7ae446991adf3d9d6102549a3faac}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga70e84a0b11a0dab64a048f8dd6bbafb2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac230813514cd9ee769f8f46b83d83f23}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga211c8274b7043802f9c746ac4f18e0fd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3b40e8e614be95d4a667a3f924ac1bb7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga89072bbdf8efacb3d243c50711f60766}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga82602c2897dd670f007aea02f3a36dc8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaab213cf8807d6e7e8b3867ffb404d763}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga625e04cf32d6c74d418ba29368f680d4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabea31cf1eca11533cd855c6bef17c829}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga61e4b1f3e82831cdc7508d4c38312eab}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9c6b66352f998564a6492d3e5d6aa536}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1384af5e720a24c083a2154c22e60391}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1e5611011911ef745b5e9d2c8d3160f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8868ab331b4bb14a1d5cc55c9133e4de}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae051ecb26de5c5b44f1827923c9837a5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b791b360bab639782613994e9ef0aa6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad1d752e67f2432510722aa5384f5cdfc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4a40356dbc0adb6d650ee2eb675de441}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga347b2b22378634cdeeef11daa132aa84}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3db2e9bae86ff5f5e376ce47599673c7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga20f05b209c652dd7105da6c3f7762b4c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac810835b2b091fbc87994052a0a8bd51}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b9075ed3e04ee9b8e624ed68ec2e3ea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6211d5b2863c7f6b86f65960f0788df1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9a6ab4a6fa25eb7b4f022ef49ce69b4a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad693d7300ed7134b60bb1a645e762358}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the APB2 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaa5393a02b936b1d6de896a6c09103a4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga932afe7cea6c567ad63e0f83308b9d3e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga840be8a915492c85d968faec688c73ea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga856c7460aa481976644736c703c6702d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2ad5daf60ee8a66825b91afa3eb7f75c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae809da64734c2dbfef1fb6ac8d00d39c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9753b09f531d9d48d31abd4f74c26d26}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga983ec0b6719bbf98e40818a8e6817c58}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7a70c26339bbcffc2ecd3d7b61066b2c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf00544b52c47b22490cd0bdf32c8ccfb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5f260959a6bfdd82918320b1b106aab2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa9eacfb8ee244074ec63dae0b9f621c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb93b1527822da05736d8fcae78597c9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae0050944298552e9f02f56ec8634f5a6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac4b142412ef1e3dab8dcf5d5f7ca4d92}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf2ccb5c6b63a60deb6463cbc629c10fe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga85678767f2c727a545b1095d9ef69a67}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga71501a0d6be9e1d0a17ff4c27a7cd8e6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f23f7c1565e07731f200059c8ed4db9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6c046db26bd6495179e6171dc6caeff3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga68c2a52fef447801cb641586a57d15e5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1f8e5c20350d611721053981830bbb12}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf2df3546bc357b952ec914f1e366a0ef}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad2b7c3a381d791c4ee728e303935832a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB2 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadbc388ef3676e37b227320df83e9d1f2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga59bd3cd20df76f885695fcdad1edce27}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga639ccb1e63662b309fc875bc608aa7e6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab1787d7cdf591c099b8d96848aee835e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga875c081e76f456494d5e06dae3581281}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab8bba755c5ee38df4fb1e27d32cada06}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga52afd021e3f0970ce10549dbfb69abac}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9cb697e01267c3ee783f0fabf3eefda1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8a762d7f473a98f820faa57284626b28}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga64dcc05f8484e6a139d0f6f4e1531fff}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacff365c1f6dd81a3c8c0d0ce571592ea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7116893adbb7fc144102af49de55350b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae8d9acd515c3fa3a3607c4d527d431c5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga22c9d59ac6062298a71eed0d6a4a9afd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0c3fd42d5fb38243e195ed04d7390672}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabd506be27916f029d2214e88bc48f6df}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac16a7c0d1778ba7cee83c45143f81c9b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa649af8007f817b25312fe2a82a2dc2d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga55adb9971771c35d36a549a1948b7b1e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf55e3121b3ce93da44a1ac83f3cdac8a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01d92a5d361dde16cf9b69e93d93f94c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6ab9ff98419017940fdd2c608e2f4db0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae613d9312d5f66a39e4d51811fb68555}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafc3ffcbb86e4913ae336ba094ca199e1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the APB4 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4411749d5b9d76cf908e26239e4b213d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabf2662a3a1baa7261e1bfa1aae10b90f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae802f53baca2b5b60de58f5ad60097d6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0eabc2676cb7daf17802807e13fc7a7d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4efc1029c8575db1e6d7515b2dea94d6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad6f0669bdae3809539ea44671e973c5f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga46597d15632e4a35f3354ed3c7f61409}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3f5e59e7d2bee567c40205a30c3d4977}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CLK\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf04a5f1f0d6d8577706022a866f4528e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa2a258a48face94f421a9bf3777e6aa7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabab1133742baef14e8d76e1b6cba9926}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae0fd2c5cf65d3bada813378c249edfe0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga17529f8824c5d76f6f0a4c27ec0b4b71}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1e161e1011e1939fad65063692d87401}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gada7ea8565860d946af577b3f35fbdfc9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac75901e8240d6a0b08db83beffddb6a1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga39f7245caab6ec7de84fd07798795853}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CLK\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad1ea95d1d5f3a2ecf2b903c4ed22e7c6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB4 peripheral clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1085236bff0042ce9f1c879f16ba27fb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac972718836d2c4e0d3bc477ee2c8a6fc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9795732f8443413d3547a85a4afb4c30}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabafe8b8e253039c455ecd51bfbd60423}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4d833e230faab6ea739dc136a0e875c7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4ffdd0a82c1de653a02a9479a757c5f4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga839b3373dde3824b421dbdeaba5013c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0a4c172888df490331077eda47ca2d89}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9f32ce5d57fe1d7a4871552d2e9a5b0e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga93fe3f9bc0b46640b63f13482637140c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf1478d44aef81f3e94f06eb3790cb94c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4bda7c78cc3917a2be8d74812dbaae5f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b7ef99ddd6b3da5a7d502bd6ad07a7c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga554076cf5205f221fb8b5abfcf5936c1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0a77adb29b138b43b6d98d721d6972f3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab46e035c47141417dacfc7b06e9cbad5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga146472a40bba8b214e3a1ea5c094033c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga230a57ed6c129076b4fd17bdb07d79f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB3\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB3 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa43472179721e30081d975b890e05a39}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5c1e90110eab6f1208d161a4a4e5052e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacc5e9454e3e387166d5caf94e91dfdf2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadb5820aecbb63af340610bab9370c544}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga200c904f6644fc13da81eed085bc6850}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae2b4b3616bb2654ac932b17e3928902e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga86ef37f424140a0f3b7f2ba868746b89}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga191d8277915b05918cc1d9a79269f025}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5ace3308265d0972961560ac0bb6c320}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87d828d91e67aaa931853a60779826c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB1\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the AHB1 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9135dece327ecc27f333f86dcf3ba8ee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0be736e6cdebf31eeded223acc25613}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab40eac923930da5e2bbe59d7d21bdac4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb9f0db40bea191227df3b9df428f97a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga23b6a1e77c4f045c29cc36a4b1e910b0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8f7eef8316c35175df11d77f5106d334}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab7d22b3d82cd2616c8e3fa930e437757}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac7a3cc8218bb6d61eba1f5a85b9bc5bd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga688618016b05c448ea8a1e7f6a6fde76}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae82cd541f933be46ec8d6c3ea50d402c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB2\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the AHB2 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6038f9dd2652e98fabd2e57e0342852d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad5f1fa1feca39e3aaa09aee9a14015b9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga18bc030f61f0fbc057786471f75373aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae5bd400860d81b996fafa310df1f2eec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3aa819914ced10bc641eadb4bda93e90}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabdd1350e70f9c77e25ea67c9929003e8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga033600fff4d5360aed69cf37584d2a76}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9d7c75f7a332eae31f8ecb3cd201db4d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB4\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the AHB4 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab329bd497cccffd979bcca9fd42bbc79}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3b89be9638638ffce3ebd4f08a3b64cf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6e6a20fa8e0d7b3ebfdce26f6b1a1ed0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0f7c49787fc94edeea74aa4218aeaf6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga00bf47b2dc642a42de9c96477db2a2c3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaddfca42e493e7c163e9decf0462183df}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf9d186d1ede1071931d87645bddb07d0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f05c575d762edf40a6d17f88671b68d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaa6a1bd3f507ece527a1b881c56d2fc2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad6f05470103a85e73fa819cb152c22d4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadb04b6621e534b40698d6e6b92d25127}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaecdd0da51c96cb11e97d0d6977f3eea5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad56e47c2eacd972491f94296053d0cc3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf03da3b36478071844fbd77df618a686}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1df0e3536d3450435bdccdbe9c878736}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga29fbf71f71ea27ffa38e7283b6dce03d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga38fcc37f656d6f5e5698d9eb01d4c552}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9f9a67f57c0ca219d0cf0c2e07114f27}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae5e39d5fdc6dee36bba521d096ca320d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaf11aa8bacb98c4e567bbaa58635acec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3342b2d378fe67eec9777df0b5546168}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7071459911285782901533c8ba08c7d2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2a445bd5c2f1e75bb54c710bf3f51e72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga63084f40abfd18f7ebe8fec367cc13cc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB3\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the APB3 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac4ec64e3a68e07e0cc6d08d0b921ea4d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa18895c87ff88482233d6cf395e80177}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+L\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the APB1 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga14baa94c3edea6bbab72d832a8e54e6f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+H\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1010b7c4a9122449860babb341f01d7b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga80ff127f3c25bde58ee5c1f224e2dca4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga16ff4de009e6cf02e8bfff068866837a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga20ca12317dd14485d79902863aad063b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3446c3ea4d5e101b591fcb0222d0fb10}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga350e60b0e21e094ff1624e1da9855e65}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1c4fa1efafbaad1e9ac513412df04f21}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac3ec3222d8441040695cb64a7be91026}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaee5b3b45c9e419c7dc2815fea8ca131f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga76cc40a6695938f9b0fb602a68a4ac31}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga869e4f5c1132e3dfce084099cf454c51}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafb0c679992eba330a2d47ac722a5c143}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga49a1b5553c9de47f520c0cb7e9451718}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab4de80173ffa0e599baab0e76d562cc3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8902e16d49b4335d213b6a115c19127b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga462f7bbb84307a5841556d43d7932d83}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga326264be9dae134e1bdccdd0161b23d1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga551c171f88af86ca985db634ac9e3275}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaed404dfdc9bc032cf718b7ed17f664f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0d824c0c76161daaefa6fd7ba2c0302}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0bc74333a544b2c4b8dc6eddd8fe5a8f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae56392937e585b8e8f2073715f4b31fe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01ea883740306b58beb1a7413bc41109}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac9bb36a0223b0dedf911cfb6fe4aeef1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga03a62cae9d5aa34f2809ec31fd0c6e36}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga285f7056b4628ec4eb05bab2ed439262}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7b583a5b7aa68cbc039d02a3cdb25e1f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1ef8a00aeccfbba36f65cb9f6c36b89f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa02c2ff6abe9d2d36bb37f51ad97b73a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7dfde454ff8311d433c54ba8abf81d25}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+L\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabec528aae84205f623c35e7408fa3a88}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+H\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4b1b3b45c95788edb29ccd2bf6994826}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga27cf9c39217fff6ae9bce2285d9aff8c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaab43d37f4682740d15c4b1fadb908d51}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf7e0cde5ea8f6425d87ebf2d91e8b360}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7eba1763b83169bc7cec3e10bfbccf20}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4451d9cbc82223d913fae1f6b8187996}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab26147981205dd120cfc129d3031459c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad95dc322d87913d9bee93a1f41ff5403}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga241bf274a6fba46a49b50aedaf1e08d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga70b1086ae23902e74a5a2a596a848430}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacb910fd0c3c5a27d020ef3df20fce4c7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1fb7a5367cfed25545058af0eb4f55f1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa34fa6ad8e85c14915f8d7d3e36fdd0b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8baebf28a2739de5f3c5ef72519b9499}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga25b71d0f7fb3b9455fb360fcb780c492}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabbfb393dffbb0652bbd581302f4de609}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7009cc550412874444d1d519b0b56b07}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87cc8c2107c1d0820cc1f7e2aeb1aeb9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2fa8cc909b285813af86c253ec110356}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga383f01978613c3b08659efab5153b4b9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6a8c5a752f83da738f47125c3d754fc9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7612487bb6026a54e42e9fe46fbd9c90}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeee4f925c087fe23254850891330c5b5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb419c2b0ac65b965ccdba4645ef9ff5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga17634ef4587b3247b81e73af7e0b32be}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae36339b1b0b08a2faafbcfd7af3021f4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga037bf7392d6912aca9ad82fa90bb6197}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac433dc93cc9d7df37b9dc56825d67452}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaed526041543102b96f321df46ba3a8df}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8788da8c644ad0cc54912baede7d49b4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB2\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the APB2 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac423d6a52fa42423119844e4a7d68c7b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabec722f05fbf534feb64a767b1bac1ba}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5db01cf30bf3c5c7fc0b42220f4c70ad}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga36242e7bdc7abbbdc33c06e72c4b45c7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87e6bc588fa1d5ce3928d2fd2a3156a4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga79eef5116f30b60d64a7ef5bce8fca05}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaff60b9ea69452692f5d15054cf45c0d5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga08cdf6a4295cfb02eae6a70aecf2e3ee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga829f154bfefa2317311c97650f1264aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac704a83b1296914d004b6c915758eaeb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga08adabe36014364464e61606606e184d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga145e3e9e6051bd665ab278f90ef7e406}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae1e413d623154942d5bbe89769161ece}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1857f223177c9548ce1bae9753e0a7b4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1eb65ddc0b32886b140d71e252dc4727}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga243061674e38d05d222697046d43813a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6b60ae1fd712732bea57de27f79a20d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad7b4bc8c8a9146529a175c45eecf25e5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8ac40732e63db2fff9e31d57b841c633}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2a3e73be86af6fa124bbd5447b732de4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaccce3b7168e4357d179cb5c978a7bfe6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga48ebe709fd10e1594c70752a05644a85}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaffa4ac19e4880063de6fe38ec07ef993}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6f43cdb59c0bf2f5315ff8a576db05ef}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6be678fc18675f06ee7dc84c96d5c10c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa2f753ddb995e36a2c2751da62833c2d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB4\+\_\+\+FORCE\+\_\+\+RESET}}()
\begin{DoxyCompactList}\small\item\em Force or release the APB4 peripheral reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga143ff27d8f59a39732efd79539e3765a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae490f9c0107ca58b2881ee5237653076}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3c63279f892ce515d74ee8facfee1345}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaced9e506d046565160936d9c9dd99270}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafaeb34a2efd7f91b417eee60045579fe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7f72dd7e26af888a3e9d5ea861c87113}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga830e19f51e822adef788129e05aac694}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga680ee80cebdcf3e1c79b59d22656ddbc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+FORCE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaccdb8e62485525ac1ec078a9174e9c43}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga56de80d50f5ab276ebdeee16a0e2a31b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2353b603aec972b0bc0afa52ce78ad42}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gadc8c017d7fa2e91725be59bd017ae940}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga97aa6b28e75f886f4aaf4a928423ba6b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga55d7026280dfc8ef6c58f573412c3c4a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaca9be6ebd880ff54875f7cad38777528}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5b2dbcf6d9afe303b6c8bf355f9e0a78}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0325ef9d7f6366680213c6842ec2281}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+RELEASE\+\_\+\+RESET}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga527ed7b397149fd6fc69d281ce39f8d8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafa223ffa1ab2f096cbadc67d6230f25b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga48733d5087a91250ee7248adc6b835b2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga387cf373f0b77ef8d434a3a6f93bbd11}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga864140e8659290a56eea3230bbb2ecc2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga34b8b55871660e1453c9a1cba26bbe16}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacc02075039fec54004eb8d44b6a25f40}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafb5213b8591abbf0de732b8531e35221}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ITCM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab1615c5c7ca332bb42e6874ddf4adfe1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D1\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE  /\texorpdfstring{$\ast$}{*} For backward compatibility \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0ac8a7117cbc4d03c18e6b3817c2dde1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga987769071231aca8feb402621a72d69d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga929bb0b8ae2f4da5481d73f265cacce0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6b5acf19e24d90165eb5bd6bee84f5be}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabe72608d1927f58cffdec6c56c51f002}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0f27a00f4e5d25cf14a70a6819c985b8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf146cdadd9f1a4dd7ce42493eb7a61b6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga73b7a67f51facccf07e2fb653d5a1292}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ITCM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2259e9075e553b5e64ad82c2b822a7c5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D1\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE      /\texorpdfstring{$\ast$}{*} For backward compatibility \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae1d931934bb3e3f9f6e42c496800a364}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5e8b096901cdeeeccac9c39b1c6753cd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa385b298d6125a8dc4fd3b49e23f0d26}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga48c04810c9a18c1a80f14361b3c421c6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8669fae9cd9180844501db82f72f3b4f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga816617af01b59bfd6e8c5f42b72233fa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3b8fff00a0e0a80f2b4f48a41c42d4f1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacc37d35d33af3f4f3967ba5100ebfc8d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ITCM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabb4fa89d88c9fcb245cf9951532350da}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa25dd2ce45cc50a194ffac5b037d76a8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabd2e91a84b9316eb88d75348fffe3852}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4695f616857083134141c3cd2e4a70fb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab0219202590eeb28176221cfdfdb0a36}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b41f06ce1b40fd1e0481be7e364e6f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5686775d5257bb3143b991dfbbf70efb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf8a57ca9ab0c284c40f98ecda6d5ae0e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DTCM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2d58397078cade84c900e152e1a59417}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ITCM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaec9e224ba424f7b02fc742b50484d18}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AXISRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga568e4d004285fe009bc4e5d33e13af61}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga16c048816a705de87bb5fd3ce4003a82}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7336fd2924664e2428c5f04a1fa75ce8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac53609690b72e5b0177fda3a5ea7887d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab96a7ad0a8f234de3bf493b8b94b6da8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8786d21490439ef0564edff087203245}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6af5c50e1a578bcc17c9514c5ab976c9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga648fe32985a490feaf13406d49cbb2c3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaca89ff50d50b87d715c9aaf57a18efd3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga35a673b52ba1ef37b7d178c2e88dab7a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2840d82c5565e7690a69a6848fa50fea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaffd54b2e17f88a7dbf9f3d30c728d8f1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaacfd31147f3f7e34f8a865f7c9acc9c8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga17e69a2906c969125f8038ae44c3fc06}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa009ac7dc7938194c7bee96502fdced2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac5b14fe76c4661619636fcdf08e2a874}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaef7e3ef7b34fec8e351c0d35a0c0b914}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf40601b803ae6495021ee70a608aad45}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga44134ce70f9ef101f60e465c6a205ba6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9246214e057bc8254d415b3d85b6039c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB1\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf6fa397bcd717325032e3425fd424988}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga03ec704e7309312630b3a572fb6f8856}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa6517155182446b08768d9b04d999109}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87889c93ead3c6df30a6245a0452c6c1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf99a20c212073269549d84bcb46db552}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga79206abe44d6019725e0c0240ec46778}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae85e4ea41a2b365ee27c459ddcb9a3a1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6858d94090ebde724466b3208505aa18}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga06ab0f05dc3d2e6494f8f33a1b20e0af}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafc915e334b12654dbee1293a1f422afe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7ddec13decdd551aa0a332fb7ca606dc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga536dc31ed0e24ad8b82f5b8c2a920b42}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga17855a8d94f794a26b7e552f98761bdb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab2a227ce9c4d9dd6572f737a35093452}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga73a8946f61c7e631f44c04f745256263}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga55238f2da587a7e788ad56c9f4015eb0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac7b5c1c60774ca2af36591d897eb352b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3e6e9992bd17add8476c9c78ab6fdf81}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga09e3b51afc877c3c070fee083d4b4b58}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5aa8207736e7fdf84282865b69879a1b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHBSRAM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaff8820b47bd3764e7cded76b9368460b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0e718efc965ab07752cd865c3f33551a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac62505cc695d985fcf18ca1fd2f1a421}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5f04963ee5709230888d50574008372f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga18d20464a11db42973a0cc6df21b0e22}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac520a0043affccd819818a11b19523a2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab1d4773e76bae0871b8dace747971fc4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3e9419b44e83ed1e6951801c390a69ad}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4b59e596f774910fdf675befd61ea83b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae1c1d324cc316103d8e0ee35fe34ecec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad0431377e09fdac4ad169bb3015f32e5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8cc3c41c9546756c91829cb28a690f9d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae18312e0b7b58cbbbff58475c75b95d8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D3\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad6753edbd9047eeac39ae4f234642942}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0a20ad851a2ef9e1ccdbf280dcd1dc44}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga293f9870ba631d23f8011bad12420f83}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8520028c77aa2ecdd497c313665fa381}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2204e5cccaf75bc541f901fd2beb7381}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga035d018d1c3984de9cc06dcb661fff60}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga296c8414e577cab553cc903752315a88}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3150a9552cca2ec7e0f00d799fc52adb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1996a49dd130e12d3524d50a926e1165}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4814e1e336da024a4136adb3a53e2b74}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8b6072932da701ed5716826ffab00478}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacfa339b4c8ec42b6934283889235cf60}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6cc356a806f7c624f800a9492c1e2a4c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D3\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabfca340e2266b35f9eb8bda9f24fb272}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae5f9c8d570ca5ce52bd3d1766ad96265}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga91d9bb261e4eb51ae5c83276ca94ba9e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9be4e7cb3610f3242eedb2c38f05cafe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaaf7c0b082ec2d976c4ac33c4f1fd461}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab2fca3cfeeeb50539e2c5702cff4d719}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6696a0a055bb4707b05e237c8a10334b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac60e430f28a40aecfc376ad9c00e94f5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga037d2c0720e41f95708e7adff6e457d9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab656df04e2f912ef03ad867c8474c59a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga684a1747a24069506d11c29e963e4282}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3984d0f524fdb339fa86dd1a7816d500}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga78d7778645b0061009e140a15657806d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D3\+SRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafb90a4c788e0b1e1dee61e462ada7f17}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2eac033c5d40d9e6eda85985322ece6f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4dd6a13690da372d5ea52476d0f972c8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafdc54fb0d223358257ea5c9f2d9c2db6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf8ff1048471b8b380eed743946d73b73}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac1d248974d2d16be159c52beb41bb648}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga965ed6d910633d0f9006e287f96bbc68}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae53e66bfd35d315af80f7d33a811de7c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga91835ace86b5463c56457f28a8bb568d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9fa340508e667c6519c6dee2e84de8ec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga609e5d6832a211eb9fb4b786dc32282f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BDMA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga58e45333355491459650af183b1bb75e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9e3e795656b8fe351274c934acc5666e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+D3\+SRAM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga375ff76fe5812805a080131198a26c5f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga218478aee9dda3df93254bb83db8fb08}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad17ddfd08db9b3e7f85417e6b3ddd99f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac36b126e0a4d17c7f5358d3ca4c63790}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga975142c90b4e1baf21b361524518235d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2e165dd342f4ab6ea9b2edab08723cf8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7911836a0e66ab2e4719b298f74b783b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae99e46f9e40655dc9b5c07b03fdc4a4e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga906c45719dcf2113473f2c3281926368}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2a1c22a18251e0dac7f77ba8398af543}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad8b3e0a9f9cb30a02d3c3e5070a9ee29}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae00ec905f6763aaaa93e6ed69afbd48c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaabdcae7edf493254fee3064775ab5023}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae4782a5ec14457be65b7329655014ef7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8a281ca72aff1c9fa87755c3854cc316}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae6fb9249362d38de5191ea0bf8bb1922}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6eaa577e71e8f881d33e2df3e3e7738e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga12132da4a7f5c62f32cd9d91b1c99495}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2a18798b0e216c3ccc3caa76e741a689}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac2ea0bded521d6ef463f543719ac6bc2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga81daeac46390e57328957a5b2d020b1b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga894dbeada170b01faef303d35de84917}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac0167c77fa1c00add900bb1cf788e68c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga989121c3284e586d4fb14549d15dc0db}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac9504845ea6557f9b54541005e2a7e07}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf79b935243146cbfeaa3c68e8083a49c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga619f901afe8c514f0782a0ab22465519}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga649a26c04fcad09ba3597c8829f8e9eb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01c12160e77cd6927939b64a90261a4b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf03dc6334b362f8768275ee55fd9b6c3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa3cc4ffe474843e54c8b354b28111a37}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gade3ce45ec47456ff982ee212d0a0f2e0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf73805f2b1d1b15745831004c975189e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga65aef0935a6eb3e1ee17e9d19ec6ee8e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf380a14a537b7a6e1c0e20fea72d65aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6d1fd6d4f7375b4abf93bd2ec4948d1d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaac91e3596950c8d33760debce6b0e416}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3dd5073cae99e103545801e21f6e25fb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga65016901a197f433425aca0a206b0c77}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga505a2a0607d8b7993e365d169aa9b53a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga329e7011f85631cd41cfaa2dc7467934}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7f7d650bc39949c0612a553fecd46fa7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5f05fa1cd35c33e8c10ee13eca75e304}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4fff9b3416d2940cac20962e6d5655ec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf53bea66d100b5039d4db0140a9948bf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7579bcc778f7c9ef723e592ea7416d0a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3ad038000c76cee2e7ca00d56ba64c17}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa395d9d235caf02cac62e5dfb1d0c957}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad07183bab161bd0524036c2dcce2ab9c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6425e05b7e3d30a060b075575740a9bb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac7dc1c5239cd70bee94eefa3d91cdd7a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga46fe2d4331320cfe49b751b5488fc0cd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6bd3af59e8a11e3321a41bc29ba51f18}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5a734374b6688f2d5e54f90d002cd634}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8fa5627785efb9a9ec810523c33b105b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaee0e23b484918cc87d4f7f902b737dae}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga10a9bf8a3752536b50ebda7a812b63f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga37f3316b0cfa308ebc3ef3aa84329ff0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87bd77e6140cca652e154d6977ef5b17}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga23945074edb08935c4d17c3580e60f0d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga62c60a404680928671a35c9063623bbe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad292d7990e0189bce51c404c4f98f5fa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf38181befdeecf6a61c03885d3645bf1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabe8c0a343d9bb288dae09aadbab028a6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga57a6fc55a53a8c9d8cc0303ec5d7177e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa32ba6dea54de9af4f8f9eaadbd90df8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8d5d8a349946a4c0698d754ee107c3cf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab1c825aefb8ae4ab199150ce061e7a8e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac4317d5e98fb245f87ecea642732c7fd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga800d326a63101506b52340cc38990f8c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa280dfb85ebcc1d58d93cb9ced93a86f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaffbc4ed076ab667f6d48b734a8d2220e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad6ee3d390b2b2748575725f5b0c42cfc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga817817bac995cdace960abeeea6a26b6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac0f75445a2e4abb6179df72dbc997b53}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga91dc6d0fdf5c1c70158336df3bf5e097}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga998cffc84c7d5866a7e4cfae1f764327}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5504a1aef7fbc81176238cc55e180e61}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga02d346b69a45b942d0e7eeb5e31d597b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga39a3efabea0fb3cffae7be7726dd668e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaffe9902aa539eca59920b6b165bd1c71}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaae09cbe8d45bdf89178a4adfed223f4b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga672f324f8570e73bd6b5e76f542d5654}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaee42b788e5d19b53922f273c8bc4a835}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga50fe316bea792eb1ae49c13445496193}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2ae6d306df3dcdc37c26446506f948c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5789d67fc7f3ba6bd9dd5f3bb422f724}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab5e167f35d61f42ae60e6cc003ee28ee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaa2baaafae70189f5ee828764fd3e0aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga886a7a99bee302cc8025968bc1132686}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga42fa6778a49adc95f45fe3a629019fad}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0a89c97a19d5057d710e475ff24b71ec}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gade73c47dc34e5841b826a0e641220801}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa138ce5c7fcfcfd42726b03e7de02c41}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaae1f723dc4b64657e58112c53514e8bc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaafa07cf3cfeac5be4071e52201dfcc7d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga64c55482f4bb2cdb236796b18c28d786}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5cc99570c53f54e236d951d4e00525ee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab81e27646b973bb95acac933c79c4522}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad93c4faee8e545c41c29bdf53aa866a6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4b5d0c823a0efc995389abaa7e8bef4a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga38ba0cbb661739ca615881f2ecfcd1c4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1cb97681bfd048c5adda494d33b18392}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9c6086aa8fadfd15c8024f9e00abe392}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad83f4e02928278fc0d9373020a82f4e0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad5c5c2cf7612ea68ae679de26f0bc26e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf8226e0579e9204a426d86d21e6c1ee0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab5d9590d92d52ff1aaa141bc565c6f84}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga133208873edc0be1774bf4f3c224a2ac}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga901cecc03cce495d9f01a7228a3bce1c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga06401c2fc03285cb8a484569d0ec2f3a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga13ddac274cda1dcd7017b16cf2bad5a9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga5d3b944dd9166218818cd1bf16076c7f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0b97aa0da40ed7519b3ddeb8267cccd8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf2de27f622cf9f740a925dcf1b533bdd}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae42efe2b704fd28cb1111dc9661be826}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7ba527b8f5c4a0cefb2aacb5a9d926f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf1816902da3b642b59136e69e6e48cc4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab435aa267105d0d86b4ea3446f1ce47f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MDIOS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4903ead1ee0b00aa284d6e8c24d3c237}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FDCAN\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6ce02f1b2689c664010bebc2363d1db4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0b7b3e090b53ddcf951239d450c5d23e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga454514918be60a95069da332eb212712}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga47fc15bdbf943a0b7164d888f1811184}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga41997855b2cc7563c8ed0c9873d32daf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf66efe83b28ede4592f8bc8c4e10b8d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3f40eb9b31422b08cb8b6bc7a9274e43}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9d7cd1e7ba9c04c2a37cf547b07a27aa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa4eb2686ca0bb9c4c816e7f708b03c1c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf0183ac6107344a8dcc43e1ab795644b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeb86a4570fd6d66626d25d45b7e9d86e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7aedb3c7d37dfaf81cd3444982990e92}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga990bf7664ac6c430c239eab292ec7ed5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga95ea11d39c41c23f619668ce078d4d8d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga75ec6abe2e15eaa24893a8cc83f4cb50}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7df7a1b0a2e5d8b9318cf68de7665b3b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2abe90eeb15890f45e28e8926bf70838}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6953cffe3f6f2c92414df6c3ff07bb95}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4e21e14c5cf621bcfc7d7cb248f5e11a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa98366992888d759ed4cd6734fd1e706}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9fd10178bcccbf50e734d39da1340cdf}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga282b97b01275b2926059e1a9469c3aef}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga443ab84b0451a65d63416c0b8750a238}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9065870baf7d1bcdaf8e3789d2a21d0e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0b265851c7557da6b372ff462819caa9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9a9f2ce9884285efd81f5fa66242cc9f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1059a391a514543547809a524b4cdf0d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7699273dbae6749ce8debf9971c72ffc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2db4e1edb831584a39e791c16edfea28}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga56ffeb3ac3595705bd1e8be895242943}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga44817c5edd50805a6a4a101c463e2578}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gacb9f81eb8d1fe44a89ac57c1fc3a5b2f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga29de4124122709afb5d1497b9de3926b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga25d02f053a40bef81c45562486cbaf8d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9104ce5c4edc990dbea591e10e221d76}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaeb7cfaffc1d33f868990e53399c38466}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga78a957797ebffd3e539bb4c833c29a3d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga605970ce7bf7802eba14e5edf27973f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2123ed8a27c8cf060899c1e7a923b8c8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3fe070ff84207cc0827889954947815d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab9a82b96c7950398956ee6f58c3d5dda}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gafaac663897775c9d6c6ed2f8dadafcf8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0dd995c3eeef42487d978242fcc9327b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9b203fb1b015bc48bd3a707654d501ba}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6907183c65e23c16e829a0a9cbeda1fb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga87122c894f691156d000537b3e963e5d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga260939535e89c796b23f9c79a23967e6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga70452f78490e8ec79583a7f20a72a300}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6e3a8ca9e554e3aa7aba57d034725655}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab94c265a4ca002e409bec72c7554cefb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga01dbcba6b868c630282dd1d257f25311}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac4953c32722168b9a7b9374a33ce322d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga458e8b510bea25ae7b8ac85227583295}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad8ed5eb87e476b99c98c7918c34b7c1d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga392c4fe607eae3a45ebd35146858669c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga45e9f2c9470e641323883e853e9105d6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga88df2fc3db08b8e36f044f9a477fc176}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga04863ff5c2174552387c549f0410df43}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaea69ea8dcb91d9778c2d917ed1f4cf47}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga11068bf054b592ea8e5b119ab0befe00}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga6f6259ffb1496dc1499503f8fb07e97c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3a0712524061bcf92235794d83a84f9c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9b663d4793c921b3d1ffce0daf3bab05}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa1a947e4280fa738b1fe5d7fd7f3a8a8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8dd40df7093d14722124999c9d163e50}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4ab0cf422d99e8e9558387a53c4f0faa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0e518b9a088d789d700d121db458403a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\begin{DoxyCompactList}\small\item\em Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabfabd5ae7c0d36c5971387ed58059f67}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa94ae1e15ebd96821bed1f8d516872f7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga06b54222bdf37fafcfa3eaf1df9c9f86}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga448c06537741a356609e5f9dfa27509e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf946200af5edff168dc7be8ea0e03b15}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga41eac71f0342b8a8c7eb590fec286e9f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab66a966201197e0ea49eb02773a30a25}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga9bfdf9d711e4cbf9f9027ddac1dbe4b4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga564fe78887dba5a7da7da1b9f2ffb372}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7710f33531a498c0def848039e06827a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga260929e1f658f1f9f7589abf0a54a903}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga73a6c540dbeb7699b176f0a86f5bce2e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga65f3f62a0fb9aa17dd0ff5e4effa5844}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabdf84d1ac3080ff253b46394c27a0a90}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2077836bb17a4f47f3d0cd43612af4a0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab1dba9ff04cc491a3d4c7730e45aa288}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+VREF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga930107f543859fab6fb3fdf3634321f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0b407a9e7c3eda603326c29e57d065e4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+STATE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable or disable peripheral bus clock when D3 domain is in DRUN. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga8850afc9537ef7183af070aa77e26481}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+HSI\+\_\+\+DIVIDER}}()
\begin{DoxyCompactList}\small\item\em Macro to get the HSI divider. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaab944f562b53fc74bcc0e4958388fd42}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the Internal High Speed oscillator (HSI). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga0c0dc8bc0ef58703782f45b4e487c031}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7bccced288554b8598110b465701fad0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI\+\_\+\+CALIBRATIONVALUE\+\_\+\+ADJUST}}(\+\_\+\+\_\+\+HSICalibration\+Value\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to adjust the Internal High Speed oscillator (HSI) calibration value. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae069a430441e0547d753a7b47feaebd1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSISTOP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaca5ca4b6c2cbd0e638b4c3b8b71cbc61}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSISTOP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga93d851ecdcd6c910044b0533261945f3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI48\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga963c000b8bce770c16acb68476919120}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSI48\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa84c473d288b2cd3f4e651ffedb24bf2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSI\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the Internal oscillator (CSI). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga38ba86c735ee6c2c84eb4a3db654dd91}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSI\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga54e1aa79a9bcfa75e52f2125d45ebb45}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSI\+\_\+\+CALIBRATIONVALUE\+\_\+\+ADJUST}}(\+\_\+\+\_\+\+CSICalibration\+Value\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro Adjusts the Internal oscillator (CSI) calibration value. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gabd28d1ef7255a06b8a2aa9d478a175df}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSISTOP\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the force of the Low-\/power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2\+Cs. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf2e8867dca9dc1487419487025317839}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CSISTOP\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga560de8b8991db4a296de878a7a8aa58b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSI\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the Internal Low Speed oscillator (LSI). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4f96095bb4acda60b7f66d5d927da181}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSI\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa3d98648399f15d02645ef84f6ca8e4b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HSE\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+STATE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the External High Speed oscillator ({\bfseries{HSE}}). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___l_s_e___configuration_ga6b2b48f429e347c1c9c469122c64798b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSE\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+STATE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the External Low Speed oscillator (LSE). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gab7cc36427c31da645a0e38e181f8ce0f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the the RTC clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaab5eeb81fc9f0c8d4450069f7a751855}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga7e10e306e7d9f3cd59d30dcb2c9cf61d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CLKPRESCALER}}(\+\_\+\+\_\+\+RTCCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macros to configure the RTC clock (RTCCLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga2b1e5349631886f29040d7a31c002718}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RTC\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RTCCLKSource\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad40d00ff1c984ebd011ea9f6e7f93c44}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+RTC\+\_\+\+SOURCE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3bf7da608ff985873ca8e248fb1dc4f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+FORCE}}()
\begin{DoxyCompactList}\small\item\em Macros to force or release the Backup domain reset. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga14f32622c65f4ae239ba8cb00d510321}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+RELEASE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaaf196a2df41b0bcbc32745c2b218e696}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the main PLL. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga718a6afcb1492cc2796be78445a7d5ab}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3b91ed3c583825f511ad281054186fee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLLCLKOUT\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL1\+Clock\+Out\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enables or disables each clock output (PLL\+\_\+\+P\+\_\+\+CLK, PLL\+\_\+\+Q\+\_\+\+CLK, PLL\+\_\+\+R\+\_\+\+CLK) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad5e1cc5aa5e64ef76506478bf3f23e1d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLLCLKOUT\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL1\+Clock\+Out\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga55ff917129b4eafb127d90ba35a0ce0e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLLFRACN\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad7afed1d1075825e286f7880b8f72dd1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLLFRACN\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga69b310a74311ec6719ab9463ecaebcb9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLLSOURCE\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLLM1\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLLN1\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLLP1\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLLQ1\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLLR1\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures the main PLL clock source, multiplication and division factors. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaf9a8466f991888332ec978dc92c62d7d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+PLLSOURCE\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+PLLSOURCE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the PLLs clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gaa7662098d7459db3e7888ed8e60c88c6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLLFRACN\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL1\+FRACN\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3c75fa8ed4bf3c61dd2ac24b41da6f6d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+VCIRANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL1\+VCIRange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL1 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga1cfc604e0630d8556dd383cf3d50b9e8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL\+\_\+\+VCORANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL1\+VCORange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL1 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gac99c2453d9e77c8b457acc0210e754c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SYSCLK\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the clock source used as system clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga32f72b8c5b7e97b415867c57f9fafed6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCLK\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SYSCLKSOURCE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the system clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga3ea1390f8124e2b3b8d53e95541d6e53}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+PLL\+\_\+\+OSCSOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the oscillator used as PLL clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___m_c_ox___clock___config_ga7e5f7f1efc92794b6f0e96068240b45e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MCO1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+MCOCLKSOURCE\+\_\+\+\_\+,  \+\_\+\+\_\+\+MCODIV\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the MCO1 clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___m_c_ox___clock___config_gabb7360422910dd65312786fc49722d25}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MCO2\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+MCOCLKSOURCE\+\_\+\+\_\+,  \+\_\+\+\_\+\+MCODIV\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the MCO2 clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gad6731530ebbbcc0696e9bd94eb0d2724}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSEDRIVE\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+LSEDRIVE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the External Low Speed oscillator (LSE) drive capability. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gada37410b216acbb9cd062f17c585517b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WAKEUPSTOP\+\_\+\+CLK\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+STOPWUCLK\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the wake up from stop clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_gae392379f2184e3e299cfe4f31d603ca3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+KERWAKEUPSTOP\+\_\+\+CLK\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+STOPKERWUCLK\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the Kernel wake up from stop clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_ga180fb20a37b31a6e4f7e59213a6c0405}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable RCC interrupt. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_gafc4df8cd4df0a529d11f18bf1f7e9f50}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable RCC interrupt. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_ga9d8ab157f58045b8daf8136bee54f139}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CLEAR\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the RCC\textquotesingle{}s interrupt pending bits. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_ga134af980b892f362c05ae21922cd828d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check the RCC\textquotesingle{}s interrupt has occurred or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_gaf28c11b36035ef1e27883ff7ee2c46b0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CLEAR\+\_\+\+RESET\+\_\+\+FLAGS}}()
\begin{DoxyCompactList}\small\item\em Set RMVF bit to clear the reset flags. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_ga80017c6bf8a5c6f53a1a21bb8db93a82}{RCC\+\_\+\+FLAG\+\_\+\+MASK}}~((uint8\+\_\+t)0x1F)
\begin{DoxyCompactList}\small\item\em Check RCC flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c___flags___interrupts___management_gae2d7d461630562bf2a2ddb31b1f96449}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c___exported___macros_ga4249cf06f1a18ad29e2e6773fc621cc5}{RCC\+\_\+\+GET\+\_\+\+PLL\+\_\+\+OSCSOURCE}}()
\item 
\#define {\bfseries HSE\+\_\+\+TIMEOUT\+\_\+\+VALUE}~\mbox{\hyperlink{stm32h7xx__hal__conf_8h_a68ecbc9b0a1a40a1ec9d18d5e9747c4f}{HSE\+\_\+\+STARTUP\+\_\+\+TIMEOUT}}
\item 
\#define {\bfseries HSI\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(2U)    /\texorpdfstring{$\ast$}{*} 2 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries HSI48\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(2U)    /\texorpdfstring{$\ast$}{*} 2 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries CSI\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(2U)    /\texorpdfstring{$\ast$}{*} 2 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries LSI\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(2U)    /\texorpdfstring{$\ast$}{*} 2 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries PLL\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(2U)    /\texorpdfstring{$\ast$}{*} 2 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries PLL\+\_\+\+FRAC\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(1U)    /\texorpdfstring{$\ast$}{*} PLL Fractional part waiting time before new latch enable \+: 1 ms \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries CLOCKSWITCH\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(5000U) /\texorpdfstring{$\ast$}{*} 5 s  \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries RCC\+\_\+\+DBP\+\_\+\+TIMEOUT\+\_\+\+VALUE}~(100U)
\item 
\#define {\bfseries RCC\+\_\+\+LSE\+\_\+\+TIMEOUT\+\_\+\+VALUE}~\mbox{\hyperlink{stm32h7xx__hal__conf_8h_a85e6fc812dc26f7161a04be2568a5462}{LSE\+\_\+\+STARTUP\+\_\+\+TIMEOUT}}
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga3da0bb3923503cb8e84e5bd75912fbb8}{IS\+\_\+\+RCC\+\_\+\+OSCILLATORTYPE}}(OSCILLATOR)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga287bbcafd73d07ec915c2f793301908a}{IS\+\_\+\+RCC\+\_\+\+HSE}}(HSE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga95d2678bf8f46e932e7cba75619a4d2c}{IS\+\_\+\+RCC\+\_\+\+LSE}}(LSE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga9d2bad5b4ad9ba8fb224ddbd949c27d6}{IS\+\_\+\+RCC\+\_\+\+HSI}}(HSI)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga87cb017c40c63651af966309b70bf88a}{IS\+\_\+\+RCC\+\_\+\+HSI48}}(HSI48)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gaaa7381dd9821c69346ce64453863b786}{IS\+\_\+\+RCC\+\_\+\+LSI}}(LSI)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gaf62b4757433d3aeb751491cf6ddc189f}{IS\+\_\+\+RCC\+\_\+\+CSI}}(CSI)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga373b85039eb8036373fe80948c153ee0}{IS\+\_\+\+RCC\+\_\+\+PLL}}(PLL)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gae1aef66aae2c0374be3c7c62d389282f}{IS\+\_\+\+RCC\+\_\+\+PLLSOURCE}}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga99e364438d03030e80e9ddcc2f964509}{IS\+\_\+\+RCC\+\_\+\+PLLRGE\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga839a2381e5e15dabdbd859c14a0fe3d2}{IS\+\_\+\+RCC\+\_\+\+PLLVCO\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga5206be7b66589b81309ee462699c6b11}{IS\+\_\+\+RCC\+\_\+\+PLLFRACN\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga8db327c085e20aeb673a9784f8508597}{IS\+\_\+\+RCC\+\_\+\+PLLM\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga12835741fbedd278ad1e91abebe00837}{IS\+\_\+\+RCC\+\_\+\+PLLN\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gad808f83505f4e802e5bafab7831f0235}{IS\+\_\+\+RCC\+\_\+\+PLLP\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gad66dbe75bf8ab2b64b200e796281a851}{IS\+\_\+\+RCC\+\_\+\+PLLQ\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga73abbfc3c2f9e5e3621a6d8321c88c3b}{IS\+\_\+\+RCC\+\_\+\+PLLR\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga07b364b5bfc3e347da9b5dbb84f81809}{IS\+\_\+\+RCC\+\_\+\+PLLCLOCKOUT\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gaedf7abbab300ed340b88d5f665910707}{IS\+\_\+\+RCC\+\_\+\+CLOCKTYPE}}(CLK)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga0797bfc445903525324cbd06a6cebbd2}{IS\+\_\+\+RCC\+\_\+\+SYSCLKSOURCE}}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga7c7dfc41a7f7f051286393bb468dabe0}{IS\+\_\+\+RCC\+\_\+\+SYSCLK}}(SYSCLK)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga6e9f1c193a2f41bcb3c2f7fa8459b5b3}{IS\+\_\+\+RCC\+\_\+\+HCLK}}(HCLK)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga94982534527278010cd63b036d38557c}{IS\+\_\+\+RCC\+\_\+\+CDPCLK1}}(CDPCLK1)
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+D1\+PCLK1}~IS\+\_\+\+RCC\+\_\+\+CDPCLK1  /\texorpdfstring{$\ast$}{*} for legacy compatibility between H7 lines \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga996af6fee7a02b51ed472e9819e9c2b8}{IS\+\_\+\+RCC\+\_\+\+PCLK1}}(PCLK1)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gae3cd45124620ae28e71fbdb91afd0c02}{IS\+\_\+\+RCC\+\_\+\+PCLK2}}(PCLK2)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga1842759b9678d7a014294edd5a9813fa}{IS\+\_\+\+RCC\+\_\+\+SRDPCLK1}}(SRDPCLK1)
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+D3\+PCLK1}~IS\+\_\+\+RCC\+\_\+\+SRDPCLK1 /\texorpdfstring{$\ast$}{*} for legacy compatibility between H7 lines\texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+RTCCLKSOURCE}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gaac2d2f9b0c3e2f4fbe2131d779080964}{IS\+\_\+\+RCC\+\_\+\+MCO}}(MCOx)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga073031d9c90c555f7874912b7e4905f6}{IS\+\_\+\+RCC\+\_\+\+MCO1\+SOURCE}}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga99f4a9acbacb5e4d2b27bb9f4f2c0a2f}{IS\+\_\+\+RCC\+\_\+\+MCO2\+SOURCE}}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga152403e1f22fd14bb9a5d86406fe593f}{IS\+\_\+\+RCC\+\_\+\+MCODIV}}(DIV)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gaa27dea5bb62b26d0881e649770252158}{IS\+\_\+\+RCC\+\_\+\+FLAG}}(FLAG)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga30ac800deb0d24eb3e2f929571e7efe8}{IS\+\_\+\+RCC\+\_\+\+HSICALIBRATION\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga059fb6f33fe25d512289cc5151962c24}{IS\+\_\+\+RCC\+\_\+\+CSICALIBRATION\+\_\+\+VALUE}}(VALUE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_ga861e69393015a4ea785b7ddd5c6e3f0c}{IS\+\_\+\+RCC\+\_\+\+STOP\+\_\+\+WAKEUPCLOCK}}(SOURCE)
\item 
\#define \mbox{\hyperlink{group___r_c_c___i_s___r_c_c___definitions_gad0dc34f195b3b9fdbf30843e3ddceee4}{IS\+\_\+\+RCC\+\_\+\+STOP\+\_\+\+KERWAKEUPCLOCK}}(SOURCE)
\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+RCC\+\_\+\+De\+Init} (void)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+RCC\+\_\+\+Osc\+Config} (\mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\+\_\+\+Osc\+Init\+Type\+Def}} \texorpdfstring{$\ast$}{*}RCC\+\_\+\+Osc\+Init\+Struct)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+RCC\+\_\+\+Clock\+Config} (const \mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\+\_\+\+Clk\+Init\+Type\+Def}} \texorpdfstring{$\ast$}{*}RCC\+\_\+\+Clk\+Init\+Struct, uint32\+\_\+t FLatency)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+MCOConfig} (uint32\+\_\+t RCC\+\_\+\+MCOx, uint32\+\_\+t RCC\+\_\+\+MCOSource, uint32\+\_\+t RCC\+\_\+\+MCODiv)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+Enable\+CSS} (void)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+Disable\+CSS} (void)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+Sys\+Clock\+Freq} (void)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+HCLKFreq} (void)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+PCLK1\+Freq} (void)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+PCLK2\+Freq} (void)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+Osc\+Config} (\mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\+\_\+\+Osc\+Init\+Type\+Def}} \texorpdfstring{$\ast$}{*}RCC\+\_\+\+Osc\+Init\+Struct)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+Get\+Clock\+Config} (\mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\+\_\+\+Clk\+Init\+Type\+Def}} \texorpdfstring{$\ast$}{*}RCC\+\_\+\+Clk\+Init\+Struct, uint32\+\_\+t \texorpdfstring{$\ast$}{*}p\+FLatency)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+NMI\+\_\+\+IRQHandler} (void)
\item 
void {\bfseries HAL\+\_\+\+RCC\+\_\+\+CSSCallback} (void)
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Header file of RCC HAL module. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 